library.tcl

proc make_PQFP208 { {prefix "IO"} } {
set element [make_element 0mm 0mm 90 3mm \
	-mark {15.3mm 15.3mm} \
	-mask-width 0.22mm \
	-pads [list pad0 {0mm 2.55mm 1.3mm 2.55mm} width 0.22mm offset {0mm 0.50mm} count 52 start 1 prefix $prefix] \
	-pads [list pad0 {2.55mm 30.6mm 2.55mm 29.3mm} width 0.22mm offset {0.50mm 0mm} count 52 start 53 prefix $prefix] \
	-pads [list pad0 {29.3mm 2.55mm 30.6mm 2.55mm} width 0.22mm offset {0mm 0.50mm} count -52 start 156 prefix $prefix] \
	-pads [list pad0 {2.55mm 0mm 2.55mm 1.3mm} width 0.22mm offset {0.50mm 0mm} count -52 start 208 prefix $prefix] \
	-rect_outline {1.30mm 1.30mm 29.30mm 29.30mm} \
	]
}

proc make_SSOP20 { {prefix "IO"} } {
# Make the pads stick out a little for easy soldering
set element [make_element 0mm 0mm 90 5mm \
	-mark {3.75mm 3.95mm} \
	-mask-width 0.27mm \
	-pads [list pad0 {0.825mm 8.4mm 0.825mm 6.425mm} width 0.27mm offset {0.65mm 0mm} count 10 start 1 prefix $prefix] \
	-pads [list pad0 {0.825mm -0.5mm 0.825mm 1.215mm} width 0.27mm offset {0.65mm 0mm} count -10 start 20 prefix $prefix] \
	-rect_outline {0mm 1.215mm 7.50mm 6.425mm} \
	]
}

proc make_AD9283 {} {
set L [make_SSOP20 "IO"]
return [name_leads $L 1 {
	PWRDWN
	VREF_OUT
	VREF_IN
	GND
	VA
	AIN-
	AIN+
	VA
	GND
	ENCODE
	D7
	D6
	D5
	D4
	VDD
	GND
	D3
	D2
	D1
	D0
	} ]
}

proc make_TQFP32 { {prefix "IO"} } {
set element [make_element 0mm 0mm 90 3mm \
	-mark {3.5mm 3.5mm} \
	-mask-width 0.27mm \
	-pads [list pad0 {0mm 1.75mm 1mm 1.75mm} width 0.27mm offset {0mm 0.5mm} count 8 start 1 prefix $prefix] \
	-pads [list pad0 {1.75mm 7mm 1.75mm 6mm} width 0.27mm offset {0.5mm 0mm} count 8 start 9 prefix $prefix] \
	-pads [list pad0 {6mm 1.75mm 7mm 1.75mm} width 0.27mm offset {0mm 0.5mm} count -8 start 24 prefix $prefix] \
	-pads [list pad0 {1.75mm 0mm 1.75mm 1mm} width 0.27mm offset {0.5mm 0mm} count -8 start 32 prefix $prefix] \
	-rect_outline {1mm 1mm 6mm 6mm} \
	]
}

proc make_MAX1444E {} {
set L [make_TQFP32 "IO"]
return [name_leads $L 1 {
	REFN
	COM
	VDD
	GND
	GND
	IN+
	IN-
	GND
	VDD
	VDD
	GND
	CLK
	PD
	GND
	~OE
	D9
	D8
	D7
	D6
	D5
	OVDD
	TP
	OGND
	D4
	D3
	D2
	D1
	D0
	REFOUT
	GND
	REFIN
	REFP
	} ]
}

proc make_QSOP16 { {prefix "IO"} } {
set element [make_element 0mm 0mm 90 3mm \
	-mark {3.1mm 2.5mm} \
	-mask-width 0.31mm \
	-pads [list pad0 {0mm 0.2775mm 1.1mm 0.2775mm} width 0.31mm offset {0mm 0.635mm} count 8 start 1 prefix $prefix] \
	-pads [list pad0 {5.1mm 0.2775mm 6.2mm 0.2775mm} width 0.31mm offset {0mm 0.635mm} count -8 start 16 prefix $prefix] \
	-rect_outline {1.1mm 0mm 5.1mm 5mm} \
	]
}

proc make_MAX4220_QSOP {} {
set L [make_QSOP16 "IO"]
return [name_leads $L 1 {
	OUTA
	INA-
	INA+
	Vcc
	INB+
	INB-
	OUTB
	} 10 {
	OUTC
	INC-
	INC+
	Vee
	IND+
	IND-
	OUTD
	} ]
}

proc make_SO14 { {prefix "IO"} } {
set element [make_element 0mm 0mm 90 3mm \
	-mark {3.1mm 4.375mm} \
	-mask-width 0.49mm \
	-pads [list pad0 {0mm 0.565mm 1.1mm 0.565mm} width 0.49mm offset {0mm 1.27mm} count 7 start 1 prefix $prefix] \
	-pads [list pad0 {5.1mm 0.565mm 6.2mm 0.565mm} width 0.49mm offset {0mm 1.27mm} count -7 start 14 prefix $prefix] \
	-rect_outline {1.1mm 0mm 5.1mm 8.75mm} \
	]
}

proc make_MAX4220 {} {
set L [make_SO14 "IO"]
return [name_leads $L 1 {
	OUTA
	INA-
	INA+
	Vcc
	INB+
	INB-
	OUTB
	OUTC
	INC-
	INC+
	Vee
	IND+
	IND-
	OUTD
	} ]
}

proc make_MAX4288 {} {
set L [make_SO14 "IO"]
return [name_leads $L 1 {
	OUTA
	INA-
	INA+
	Vee
	} 6 {
	~DISABLEA
	} 9 {
	~DISABLEB
	} 11 {
	INB+
	INB-
	OUTB
	Vcc
	} ]
}

proc make_SO8 { {prefix "IO"} } {
# Make the pads stick out a little for easy soldering
set element [make_element 0mm 0mm 90 3mm \
	-mark {3.1mm 2.5mm} \
	-mask-width 0.483mm \
	-pads [list pad0 {-0.5mm 0.595mm 1.1mm 0.595mm} width 0.483mm offset {0mm 1.27mm} count 4 start 1 prefix $prefix] \
	-pads [list pad0 {5.1mm 0.595mm 6.7mm 0.595mm} width 0.483mm offset {0mm 1.27mm} count -4 start 8 prefix $prefix] \
	-rect_outline {1.1mm 0mm 5.1mm 5mm} \
	-circle_outline {1.5mm -0.5mm 0.2mm } \
	]
}

proc make_LTC1763CS {} {
set L [make_SO8 "IO"]
return [name_leads $L 1 {
	OUT
	SENSE
	GND
	BYPASS
	~SHDN
	GND
	GND
	IN
	} ]
}

proc make_SO16 { {prefix "IO"} } {
# Make the pads stick out a little for easy soldering
set element [make_element 0mm 0mm 90 3mm \
	-mark {3.1mm 2.5mm} \
	-mask-width 0.483mm \
	-pads [list pad0 {-0.5mm 0.595mm 1.1mm 0.595mm} width 0.483mm offset {0mm 1.27mm} count 8 start 1 prefix $prefix] \
	-pads [list pad0 {5.1mm 0.595mm 6.7mm 0.595mm} width 0.483mm offset {0mm 1.27mm} count -8 start 16 prefix $prefix] \
	-rect_outline {1.1mm 0mm 5.1mm 10mm} \
	-circle_outline {1.5mm -0.5mm 0.2mm } \
	]
}

proc make_LTC1763CS {} {
set L [make_SO16 "IO"]
return [name_leads $L 1 {
	B1
	A1
	OUT1
	EN
	OUT2
	A2
	B2
	GND
	B3
	A3
	OUT3
	NEG_EN
	OUT4
	A4
	B4
	VDD
	} ]
}

proc make_PDIP8 { prefix } {
# hole needs to be 1mm+allow for plating
set hole 44mil
set diameter 2.15mm
set element [make_element 0mm 0mm 90 3mm \
	-mark {4.7mm 4.73mm} \
	-pins [list pin0 {0mm 0.92mm} diameter $diameter hole $hole offset {0mm 2.54mm} count 4 start 1 mark 1 prefix $prefix] \
	-pins [list pin0 {9.40mm 0.92mm} diameter $diameter hole $hole offset {0mm 2.54mm} count -4 start 8 prefix $prefix] \
	-rect_outline {1.525mm 0mm 7.875mm 9.46mm} \
	-circle_outline {1.5mm -0.5mm 0.2mm } \
	]
}

proc make_24LC64 {} {
set L [make_PDIP8 "IO"]
return [name_leads $L 1 {
	A0
	A1
	A2
	Vss
	SDA
	SCL
	WP
	Vcc
	} ]
}

proc make_xtal {} {
set element [make_element 0mm 0mm 90 3mm \
	-mark {2.25mm 5.5mm} \
	-pins [list pin0 {2.25mm 3mm} diameter 2mm hole 44mil offset {0mm 5mm} count 2 start 1 prefix "PIN"] \
	-rect_outline {0mm 0mm 4.5mm 11mm} \
	]
return $element
}

proc make_TQFP100 { prefix } {
# Make pads stick out a little for easy soldering
set element [make_element 0mm 0mm 90 3mm \
	-mark {8mm 11mm} \
	-pads [list pad0 {-0.5mm 1.575mm 1mm 1.575mm} width 0.3mm offset {0mm 0.65mm} count 30 start 1 prefix $prefix] \
	-pads [list pad0 {1.825mm 22.5mm 1.825mm 21mm} width 0.3mm offset {0.65mm 0mm} count 20 start 31 prefix $prefix] \
	-pads [list pad0 {15mm 1.575mm 16.5mm 1.575mm} width 0.3mm offset {0mm 0.65mm} count -30 start 80 prefix $prefix] \
	-pads [list pad0 {1.825mm -0.5mm 1.825mm 1mm} width 0.3mm offset {0.65mm 0mm} count -20 start 100 prefix $prefix] \
	-rect_outline {1mm 1mm 15mm 21mm} \
	]
}

proc make_CY7C68013 {} {
set L [make_TQFP100 "IO"]
return [name_leads $L 1 {
	VCC
	GND
	RDY0
	RDY1
	RDY2
	RDY3
	RDY4
	RDY5
	AVCC
	XTALOUT
	XTALIN
	AGND
	} 16 {
	VCC
	DPLUS
	DMINUS
	GND
	VCC
	GND
	INT4
	TO
	T1
	T2
	IFCLK
	RESERVED
	BKPT
	SCL
	SDA
	~RD
	~WR
	VCC
	PB0
	PB1
	PB2
	PB3
	VCC
	GND
	TxD0
	RxD0
	TxD1
	RxD1
	PB4
	PB5
	PB6
	PB7
	GND
	VCC
	GND } 51 {
	CTL3
	CTL4
	VCC
	CTL0
	CTL1
	CTL2
	PC0
	PC1
	PC2
	PC3
	PC4
	PC5
	PC6
	PC7
	GND
	VCC
	PA0
	PA1
	PA2
	PA3
	PA4
	PA5
	PA6
	PA7
	GND
	CTL5
	~RESET
	VCC
	WAKEUP
	PD0 } 81 {
	PD1
	PD2
	PD3
	~INT5
	VCC
	PE0
	PE1
	PE2
	PE3
	PE4
	PE5
	PE6
	PE7
	GND
	PD4
	PD5
	PD6
	PD7
	GND
	CLKOUT
	} ]
}

proc make_usb_b_connector {} {
set element [make_element 0mm 0mm 90 3mm \
	-mark {8.2mm 7.17mm} \
	-pins [list pin0 {10.40mm 1.15mm} diameter 6mm hole 96mil offset {0mm 12.04mm} count 2 start 5 prefix "SHELL"] \
	-pins [list pin0 {13.11mm 5.92mm} diameter 1.6mm hole 36mil offset {0mm 2.50mm} count -2 start 4 prefix "PIN"] \
	-pins [list pin0 {15.11mm 5.92mm} diameter 1.6mm hole 36mil offset {0mm 2.50mm} count 2 start 1 prefix "PIN"] \
	-rect_outline {0mm 1.17mm 16.4mm 13.17mm} \
	]
return [name_leads $element 1 {
	V+
	D-
	D+
	GND
	GND
	GND
	} ]
}

proc make_SOT23 { prefix } {
set element [make_element 0mm 0mm 90 3mm \
	-mark {1.09mm 1.475mm} \
	-pads [list pad0 {0.2mm 1.475mm -1mm 1.475mm} width 1mm offset {0mm 0mm} count 1 start 1 prefix $prefix] \
	-pads [list pad0 {2.0mm 0.54mm 3mm 0.54mm} width 1mm offset {0mm 1.91mm} count 2 start 2 prefix $prefix] \
	-rect_outline {0mm 0mm 2.18mm 2.95mm} \
	]
return $element
}

proc make_ESD_supp {} {
set L [make_SOT23 "IO"]
return [name_leads $L 1 {
	GND
	PIN1
	PIN2
	} ]
}

# LEDs, small caps, etc
proc make_t1 {} {
set element [make_element 0mm 0mm 90 50mil \
	-mark {100mil 100mil} \
	-pins [list pin0 {50mil 100mil} diameter 2mm hole 36mil offset {100mil 0mm} count 2 start 1 mark 1 prefix ""] \
	-circle_outline {100mil 100mil 100mil} \
	]
return [name_leads $element 1 {
	C+
	C-
	} ]
}

proc make_small_elec_cap {} {
set element [make_element 0mm 0mm 90 3mm \
	-mark {4mm 4mm} \
	-pins [list pin0 {2mm 4mm} diameter 2mm hole 36mil offset {4mm 0mm} count 2 start 1 mark 1 prefix ""] \
	-circle_outline {4mm 4mm 4mm} \
	]
return [name_leads $element 1 {
	C+
	C-
	} ]
}

proc make_small_cap {} {
set element [make_element 0mm 0mm 90 3mm \
	-mark {4mm 4mm} \
	-pins [list pin0 {2mm 4mm} diameter 2mm hole 36mil offset {4mm 0mm} count 2 start 1 prefix ""] \
	-circle_outline {4mm 4mm 4mm} \
	]
return $element
}

proc make_small_resistor { {length 10mm } } {
set element [make_element 0mm 0mm 0 0mm \
	-mark [list 1.5mm [expr [dim2mil $length]/2+[dim2mil 1mm]]] \
	-pins [list pin0 {1.5mm 1mm} diameter 2mm hole 36mil offset [list 0mm $length] count 2 start 1 prefix ""] \
	-rect_outline [list 0mm 0mm 3mm [expr [dim2mil $length]+[dim2mil 2mm]]] \
	]
return $element
}

proc make_vert_res {} {
set element [make_element 0mm 0mm 90 3mm \
	-mark {4mm 4mm} \
	-pins [list pin0 {2mm 4mm} diameter 2mm hole 36mil offset {4mm 0mm} count 2 start 1 prefix ""] \
	-rect_outline {0mm 2mm 8mm 6mm} \
	]
return $element
}

proc make_vert_diode {} {
set element [make_element 0mm 0mm 90 3mm \
	-mark {4mm 4mm} \
	-pins [list pin0 {2mm 4mm} diameter 2mm hole 36mil offset {4mm 0mm} count 2 start 1 mark 1 prefix ""] \
	-rect_outline {0mm 2mm 8mm 6mm} \
	-line {8.5mm 4mm 9.5mm 4mm} \
	-line {9mm 3.5mm 9mm 4.5mm} \
	]
return $element
}

proc make_large_diode {} {
set element [make_element 0mm 0mm 90 0mm \
	-mark {11mm 4mm} \
	-pins [list pin0 {2mm 4mm} diameter 4mm hole 2mm offset {18mm 0mm} count 2 start 1 mark 1 prefix ""] \
	-rect_outline {0mm 2mm 22mm 6mm} \
	-line {22.5mm 4mm 23.5mm 4mm} \
	-line {23mm 3.5mm 23mm 4.5mm} \
	]
return $element
}

proc make_1206 {} {
set element [make_element 0mm 0mm 90 2mm \
	-mask-width 1.3mm \
	-mark {2.5mm 0.8mm} \
	-pads [list pad0 {0.65mm 0.65mm 0.65mm 0.65mm} width 2mm offset {3.5mm 0mm} count 2 start 1 prefix ""] \
	-rect_outline {-0.7mm -0.7mm 5.5mm 2mm} \
	]
return $element
}

proc make_0805 {} {
set element [make_element 0mm 0mm 90 2mm \
	-mask-width 1.3mm \
	-copper-width 1.3mm \
	-mark {1.70mm 0.75mm} \
	-pads [list pad0 {0.65mm 0.65mm 0.65mm 0.65mm} width 1.5mm offset {2.3mm 0mm} count 2 start 1 prefix ""] \
	-rect_outline {-0.5mm -0.5mm 4.1mm 1.75mm} \
	]
return $element
}

proc make_0603 {} {
set element [make_element 0mm 0mm 90 1.5mm \
	-mark {1.70mm 0.75mm} \
	-mask-width 0.8mm \
	-copper-width 1mm \
	-pads [list pad0 {0.5mm 0.5mm 0.5mm 0.5mm} width 0.8mm offset {1.25mm 0mm} count 2 start 1 prefix ""] \
	-rect_outline {-0.1mm -0.1mm 2.60mm 1.1mm} \
	]
return $element
}

proc make_test_point_block { N M {diameter 2.15mm} {hole 43mil} } {
# in mm
set delta [dim2mil 100mil]
# hole needs to be 1mm+allow for plating
set diameter [dim2mil $diameter]
set width [expr ($N-1)*$delta+$diameter+1]
set height [expr ($M-1)*$delta+$diameter+1]
set L {}
for { set i 0 } { $i < $M } { incr i } {
	lappend L -pins [list pin0 "[expr ($diameter+1)/2.0] [expr $i*$delta+($diameter+1)/2.0]" diameter ${diameter} hole ${hole} offset "${delta} 0" count $N mark 1 start [expr $i*$N+1]]
	}
set element [eval make_element 0mm 0mm 90 3mm \
	-mark "{[expr $width/2.0] [expr $height/2.0]}" \
	$L \
	-rect_outline "{0 0 ${width} ${height}}" \
	]
return $element
}

proc make_terminal_block2 {} {
# hole needs to be 1mm+allow for plating
set element [make_element 0mm 0mm 90 3mm \
	-mark {3.75mm 5mm} \
	-pins [list pin0 {4mm 2.5mm} diameter 3.5mm hole 1.5mm offset {0mm 5mm} count 2 start 1 mark 1] \
	-rect_outline {0mm 0mm 7.5mm 10mm} \
	]
return $element
}

proc make_terminal_block3 {} {
# hole needs to be 1mm+allow for plating
set element [make_element 0mm 0mm 90 7mm \
	-mark {4mm 7.5mm} \
	-pins [list pin0 {4mm 2.5mm} diameter 3.5mm hole 1.5mm offset {0mm 5mm} count 3 start 1 mark 1] \
	-rect_outline {0mm 0mm 7.5mm 15mm} \
	]
return $element
}

proc make_50_pin { {diameter 66mil} } {
return [make_test_point_block 25 2 $diameter]
}

proc make_hirose_fx2 {count {hole 43mil} } {
# we have 4 rows of pins
set count [expr $count/4]
set element [make_element 0mm 0mm 90 4mm \
	-mark {3.75mm 5mm} \
	-pins [list pin0 {6.58mm 0.5mm} diameter 68mil hole $hole offset {2.54mm 0mm} count $count start [expr 2*$count-1] prefix "B" step -2] \
	-pins [list pin0 {5.31mm 2.405mm} diameter 68mil hole $hole offset {2.54mm 0mm} count $count start [expr 2*$count] prefix "B" step -2] \
	-pins [list pin0 {6.58mm 4.310mm} diameter 68mil hole $hole offset {2.54mm 0mm} count $count start [expr 2*$count-1] prefix "A" step -2] \
	-pins [list pin0 {5.31mm 6.215mm} diameter 68mil hole $hole offset {2.54mm 0mm} count $count start [expr 2*$count] prefix "A" step -2] \
	-rect_outline [list 0mm -1.5mm [expr $count*2.54+10.62]mm 8.5mm] \
	-rect_outline [list 0mm -7.5mm [expr $count*2.54+10.62]mm 8.5mm] \
	]
return $element
}

proc make_RU16 { prefix } {
set element [make_element 0mm 0mm 90 3mm \
	-mask-width 0.31mm \
	-mark {3.2mm 2.5mm} \
	-pads [list pad0 {0mm 0.2775mm 2.1mm 0.2775mm} width 0.31mm offset {0mm 0.65mm} count 8 start 1 prefix $prefix] \
	-pads [list pad0 {6.1mm 0.2775mm 8.2mm 0.2775mm} width 0.31mm offset {0mm 0.65mm} count -8 start 16 prefix $prefix] \
	-rect_outline {2.1mm 0mm 6.1mm 5mm} \
	]
}

proc make_AD8369 {} {
set L [make_RU16 ""]
return [name_leads $L 1 {
	INLO
	GND
	BIT0
	BIT1
	BIT2
	BIT3
	DENB
	OPLO
	OPHI
	CMDC
	FILT
	SENB
	VPOS
	PWUP
	GND
	INHI
	} ]
}

#
# TSSOP
#
proc make_PCA9539PW {} {
set L [make_element 0mm 0mm 90 3mm \
	-mask-width 0.31mm \
	-mark {3.2mm 2.5mm} \
	-pads [list pad0 {0mm 0.2775mm 1.1mm 0.2775mm} width 0.31mm offset {0mm 0.65mm} count 12 start 1 prefix ""] \
	-pads [list pad0 {5.1mm 0.2775mm 6.2mm 0.2775mm} width 0.31mm offset {0mm 0.65mm} count -12 start 24 prefix ""] \
	-rect_outline {1.1mm 0mm 5.1mm 5mm} \
	]

return [name_leads $L 1 {
	INT
	A1
	RESET
	IO00
	IO01
	IO02
	IO03
	IO04
	IO05
	IO06
	IO07
	GND

	IO10
	IO11
	IO12
	IO13
	IO14
	IO15
	IO16
	IO17
	A0
	SCL
	SDA
	VDD
	} ]
}

#
# SO24
#
proc make_PCA9539D {} {
set L [make_element 0mm 0mm 270 11.5mm \
	-mask-width 0.49mm \
	-mark {3.1mm 4.375mm} \
	-pads [list pad0 {0mm 0.565mm 2.1mm 0.565mm} width 0.49mm offset {0mm 1.27mm} count 12 start 1 prefix ""] \
	-pads [list pad0 {9.7mm 0.565mm 11.8mm 0.565mm} width 0.49mm offset {0mm 1.27mm} count -12 start 24 prefix ""] \
	-rect_outline {2.1mm 0mm 9.7mm 15mm} \
	]

return [name_leads $L 1 {
	INT
	A1
	RESET
	IO00
	IO01
	IO02
	IO03
	IO04
	IO05
	IO06
	IO07
	GND

	IO10
	IO11
	IO12
	IO13
	IO14
	IO15
	IO16
	IO17
	A0
	SCL
	SDA
	VDD
	} ]
}

proc make_TI_SSOP48 { prefix } {
# Make the pads stick out a little for easy soldering
set element [make_element 0mm 0mm 90 5mm \
	-mark {3.75mm 3.95mm} \
	-mask-width 0.27mm \
	-pads [list pad0 {0.825mm 11.6mm 0.825mm 9.6mm} width 0.34mm offset {0.635mm 0mm} count 24 start 1 prefix $prefix] \
	-pads [list pad0 {0.825mm 0mm 0.825mm 2mm} width 0.34mm offset {0.635mm 0mm} count -24 start 48 prefix $prefix] \
	-rect_outline { 0mm 5.5mm 1.2mm 5.11mm} \
	]
return $element
}

proc make_DAC7634 {} {
set L [make_TI_SSOP48 "IO"]
return [name_leads $L 1 {
	NC1
	NC2
	SDI
	DGND
	CLK
	DGND
	LDAC
	DGND
	LOAD_NEG
	DGND
	CS_NEG
	DGND
	SDO
	DGND
	RSTSEL
	DGND
	RST
	DGND
	NC19
	NC20
	DGND
	DGND
	VDD
	VDD

	VOUT_A_sense
	VOUT_A
	AGND
	VSS
	VREF_L_AB_sense
	VREF_L_AB
	VREF_H_AB
	VREF_H_AB_sense
	VOUT_B_sense
	VOUT_B
	VOUT_C_sense
	VOUT_C
	VREF_H_CD_sense
	VREF_H_CD
	VREF_L_CD
	VREF_L_CD_sense
	VOUT_D_sense
	VOUT_D
	VSS
	VSS
	AGND
	AGND
	VCC
	VCC
	} ]
}

proc make_TI_MSOP8 { prefix } {
set element [make_element 0mm 0mm 90 3mm \
	-mark {1.09mm 1.475mm} \
	-pads [list pad0 {0mm 0.54mm 1.5mm 0.54mm} width 0.38mm offset {0mm 0.65mm} count 4 start 1 prefix $prefix] \
	-pads [list pad0 {4.5mm 0.54mm 6mm 0.54mm} width 0.38mm offset {0mm 0.65mm} count -4 start 8 prefix $prefix] \
	-rect_outline {2.7mm -0.4mm 3.3mm 0.8mm} \
	]
return $element
}

proc make_ref50xx {} {
set L [make_TI_MSOP8 "IO"]
return [name_leads $L 1 {
	NC1
	VIN
	TEMP
	GND
	TRIM
	VOUT
	NC7
	NC8
	} ]
}

proc make_ADR44x {} {
set L [make_SO8 "IO"]
return [name_leads $L 1 {
	TP1
	VIN
	NC3
	GND
	TRIM
	VOUT
	NC7
	TP2
	} ]
}


proc make_TI_TSSOP24 {prefix} {
set element [make_element 0mm 0mm 90 3mm \
	-mask-width 0.31mm \
	-mark {3.2mm 2.5mm} \
	-pads [list pad0 {0mm 0.2775mm 1.6mm 0.2775mm} width 0.31mm offset {0mm 0.65mm} count 12 start 1 prefix ""] \
	-pads [list pad0 {6mm 0.2775mm 7.6mm 0.2775mm} width 0.31mm offset {0mm 0.65mm} count -12 start 24 prefix ""] \
	-rect_outline {3.5mm -0.4mm 4.11mm 0.8mm} \
	]
return $element
}

proc make_PGA280 {} {
set L [make_TI_TSSOP24 "IO"]

return [name_leads $L 1 {
	VON
	VOP
	VOCM
	VSOP
	VSON
	VSP
	INP2
	INN2
	INP1
	INN1
	VSN
	DGND

	DVDD
	SDO
	SDI
	SCLK
	CS_NEG
	GPIO6
	GPIO5
	GPIO4
	GPIO3
	GPIO2
	GPIO1
	GPIO0
	} ]
}

proc make_TI_TSSOP16 {prefix} {
set element [make_element 0mm 0mm 90 3mm \
	-mask-width 0.31mm \
	-mark {3.2mm 2.5mm} \
	-pads [list pad0 {0mm 0.2775mm 1.6mm 0.2775mm} width 0.31mm offset {0mm 0.65mm} count 8 start 1 prefix ""] \
	-pads [list pad0 {6mm 0.2775mm 7.6mm 0.2775mm} width 0.31mm offset {0mm 0.65mm} count -8 start 16 prefix ""] \
	-rect_outline {3.5mm -0.4mm 4.11mm 0.8mm} \
	]
return $element
}

proc make_ADS1271 {} {
set L [make_TI_TSSOP16 "IO"]

return [name_leads $L 1 {
	AINP
	AINN
	AGND
	AVDD
	MODE
	FORMAT
	SYNC_NEG
	DIN

	DOUT
	DRDY_NEG
	SCLK
	CLK
	DVDD
	DGND
	VREFN
	VREFP
	} ]
}

proc make_to220 {} {
# hole needs to be 1mm+allow for plating
set element [make_element 0mm 0mm 90 3mm \
	-mark {1.55mm 4.125mm} \
	-pins [list pin0 {1.55mm 1.55mm} diameter 2mm hole 1mm offset {0mm 2.55mm} count 3 start 1] \
	-rect_outline {0mm 0mm 3.1mm 8.25mm} \
	-line {3.5mm -1mm 3.5mm 9.25mm} \
	]
return $element
}


proc make_lm338 {} {
return [name_leads [make_to220] 1 {
	VADJ
	VOUT
	VIN
	} ]
}

proc make_to3p {} {
# hole needs to be 1mm+allow for plating
set element [make_element 0mm 0mm 90 7mm \
	-mark {2.5mm 7.9mm} \
	-pins [list pin0 {2.5mm 2.45mm} diameter 3mm hole 1.5mm offset {0mm 5.45mm} count 3 start 1] \
	-rect_outline {0mm 0mm 5mm 15.8mm} \
	-line {5.5mm -2mm 5.5mm 17.8mm} \
	]
return $element
}

proc make_fja4310 {} {
return [name_leads [make_to3p] 1 {
	BASE
	COLLECTOR
	EMITTER
	} ]
}

proc make_hole { {hole 3.5mm} {ring 3mm} {gap 1mm} } {
set ring_mils [dim2mil $ring]
set radius [expr round(0.5+0.5*([dim2mil $hole]+$ring_mils+[dim2mil $gap]))]
set size [expr 2*$radius]
set element [make_element 0mm 0mm 90 $size \
	-mask-width 0.31mm \
	-mark [list $radius $radius] \
	-pins [list pin0 [list $radius $radius] diameter [expr [dim2mil $ring]+[dim2mil $hole]] hole $hole offset {0mm 0mm} count 1 start 1] \
	-rect_outline [list 0 0 $size $size] \
	-line [list [expr $radius-$ring_mils] $radius [expr $radius+$ring_mils] $radius] \
	-line [list $radius [expr $radius-$ring_mils] $radius [expr $radius+$ring_mils] ] \
	]
return $element
}

proc make_thermal { layer style pin_spec {width 2mm} } {
PUSH_SETTINGS
DEFAULT_LAYER $layer
DEFAULT_STYLE $style
DEFAULT_FLAG line ""
MAKE_PATH [LEAD_CENTER $pin_spec] [list NW$width SE$width SE$width NW$width] [LEAD_CENTER $pin_spec]
MAKE_PATH [LEAD_CENTER $pin_spec] [list NE$width SW$width SW$width NE$width] [LEAD_CENTER $pin_spec]
POP_SETTINGS
}

proc make_via_thermal { layer style pin_spec {width 1mm}} {
PUSH_SETTINGS
DEFAULT_LAYER $layer
DEFAULT_STYLE $style
DEFAULT_FLAG line ""
MAKE_PATH [VIA_CENTER $pin_spec] [list N$width S$width S$width N$width] [VIA_CENTER $pin_spec]
MAKE_PATH [VIA_CENTER $pin_spec] [list E$width W$width W$width E$width] [VIA_CENTER $pin_spec]
POP_SETTINGS
}

proc make_thermal_h { layer style pin_spec {width 2mm}} {
PUSH_SETTINGS
DEFAULT_LAYER $layer
DEFAULT_STYLE $style
DEFAULT_FLAG line ""
MAKE_PATH [LEAD_CENTER $pin_spec] [list E$width W$width W$width E$width] [LEAD_CENTER $pin_spec]
POP_SETTINGS
}

proc make_thermal_v { layer style pin_spec {width 2mm} } {
PUSH_SETTINGS
DEFAULT_LAYER $layer
DEFAULT_STYLE $style
DEFAULT_FLAG line ""
MAKE_PATH [LEAD_CENTER $pin_spec] [list S$width N$width N$width S$width] [LEAD_CENTER $pin_spec]
POP_SETTINGS
}


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