carrier_board.tcl
global skip_missed_pins
set skip_missed_pins 1
#
# Unspecified dimensions are in 1/100 mil
#
source "library.tcl"
PCB "lvdt_interface1" 16in 5.3in
DRC space 10mil width 12mil overlap 5mil silkwidth 8mil
#
# The board uses only 2 layers, however pcb wants two extra for silk and rat lines
#
LAYERS total 4 solder {1} component {2} names {
1 "solder"
2 "component"
}
#STYLE "Signal" thickness 11mil diameter 60mil hole 36mil
STYLE "Signal" thickness 12mil diameter 48mil hole 24mil
STYLE "Power" thickness 1mm diameter 60mil hole 36mil
STYLE "Fat" thickness 25mil diameter 60mil hole 36mil
STYLE "Skinny" thickness 10mil diameter 36mil hole 24mil
STYLE "Signal_via" thickness 12mil diameter 36mil hole 20mil
#
# Use ${prefix}_POWER_INPUT*2 for input, ${prefix}_POWER_OUTPUT*2 for output
#
proc lm_positive_power { prefix x y net_input net_output {lm_chip LM340} } {
PUSH_SETTINGS
MOVE_OFFSET $x $y
DEFAULT_STYLE "Power"
DEFAULT_LAYER "solder"
MAKE_RECT {0mm 0mm} {35mm 30mm}
DEFAULT_LAYER "component"
PART "${prefix}_POWER_INPUT" "Power input" 32mm 2.5mm 90 [make_test_point_block 2 1]
make_thermal_h "solder" "Power" "${prefix}_POWER_INPUT*1"
PART "${prefix}_POWER_OUTPUT" "Power output" 3mm 2.5mm 90 [make_test_point_block 2 1]
make_thermal_h "solder" "Power" "${prefix}_POWER_OUTPUT*1"
PART "${prefix}_REG" $lm_chip 15mm 15mm 0 [make_to220]
make_thermal_h "solder" "Power" "${prefix}_REG*2"
PART "${prefix}_H0" "H0" 20mm 2.3mm 0 [make_hole 3.7mm 3mm 0.9mm]
PART "${prefix}_H1" "H1" 20mm 27.7mm 0 [make_hole 3.7mm 3mm 0.9mm]
make_thermal_h "solder" "Power" "${prefix}_H0*1" 5mm
make_thermal_h "solder" "Power" "${prefix}_H1*1" 5mm
#DEFAULT_LAYER "solder"
#MAKE_PATH [LEAD_CENTER "${prefix}_H0*1"] {E5mm W10mm E5mm} [LEAD_CENTER "${prefix}_H0*1"]
#MAKE_PATH [LEAD_CENTER "${prefix}_H1*1"] {E5mm W10mm E5mm} [LEAD_CENTER "${prefix}_H1*1"]
#
# Use an LED for debugging and as a default load
#
PART "${prefix}_r1" "r1" 4mm 8mm 0 [make_0805]
PART "${prefix}_L1" "L1" 10mm 100mil 90 [make_t1]
make_thermal_h "solder" "Power" "${prefix}_L1*1"
CONNECT "$net_output" [list "${prefix}_r1*1" "${prefix}_POWER_OUTPUT*2" "${prefix}_REG*3"]
CONNECT "$net_input" [list "${prefix}_POWER_INPUT*2" ]
CONNECT "GND" [list "${prefix}_L1*1" "${prefix}_POWER_OUTPUT*1" "${prefix}_POWER_INPUT*1" "${prefix}_REG*2" "${prefix}_H0*1" "${prefix}_H1*1"]
CONNECT "${prefix}_LED1" [list "${prefix}_r1*2" "${prefix}_L1*2"]
MAKE_PATH [LEAD_CENTER "${prefix}_r1*2"] { EN } [LEAD_CENTER "${prefix}_L1*2"]
# Bypass capacitors
PART "${prefix}_c1" "c1" 11mm 12mm -90 [make_0805]
PART "${prefix}_c2" "c2" 31mm 18mm 0 [make_small_elec_cap]
make_thermal_h "solder" "Power" "${prefix}_c2*1"
PART "${prefix}_c3" "c3" 31mm 26mm 0 [make_small_elec_cap]
make_thermal_h "solder" "Power" "${prefix}_c3*1"
PART "${prefix}_c4" "c4" 11mm 16.5mm 90 [make_0805]
PART "${prefix}_c5" "c5" 4mm 20mm -90 [make_small_elec_cap]
make_thermal_h "solder" "Power" "${prefix}_c5*1"
PART "${prefix}_c6" "c6" 10mm 26mm -90 [make_small_elec_cap]
make_thermal_h "solder" "Power" "${prefix}_c6*1"
PART "${prefix}_c7" "c6" 5mm 12mm 180 [make_1206]
PART "${prefix}_r2" "r2" 32mm 10mm 90 [make_vert_res]
MOVE_LABEL "${prefix}_c1" 0mm -5mm
MOVE_LABEL "${prefix}_c4" 0mm 5mm
MAKE_PATH [LEAD_CENTER "${prefix}_REG*1"] S [LEAD_CENTER "${prefix}_c1*2"]
MAKE_PATH [LEAD_CENTER "${prefix}_c1*1"] S [LEAD_CENTER "${prefix}_c4*1"]
MAKE_PATH [LEAD_CENTER "${prefix}_c7*1"] {S W} [LEAD_CENTER "${prefix}_c4*1"]
MAKE_PATH [LEAD_CENTER "${prefix}_REG*2"] {E S} [LEAD_CENTER "${prefix}_c4*1"]
MAKE_PATH [LEAD_CENTER "${prefix}_REG*3"] {E S} [LEAD_CENTER "${prefix}_c6*2"]
MAKE_PATH [LEAD_CENTER "${prefix}_REG*1"] {W S} [LEAD_CENTER "${prefix}_c3*2"]
for { set i 1 } { $i <= 7 } { incr i } {
CONNECT "GND" [list "${prefix}_c$i*1"]
}
CONNECT $net_input [list "${prefix}_r2*1" ]
CONNECT "${prefix}_in" [list "${prefix}_c1*2" "${prefix}_c2*2" "${prefix}_c3*2" "${prefix}_r2*2" "${prefix}_REG*1"]
CONNECT $net_output [list "${prefix}_c4*2" "${prefix}_c5*2" "${prefix}_c6*2" "${prefix}_c7*2"]
MAKE_PATH [LEAD_CENTER "${prefix}_POWER_INPUT*2"] {S W} [LEAD_CENTER "${prefix}_r2*1"]
MAKE_PATH [LEAD_CENTER "${prefix}_r2*2"] {S W} [LEAD_CENTER "${prefix}_REG*1"]
MAKE_PATH [LEAD_CENTER "${prefix}_POWER_OUTPUT*2"] {S E} [LEAD_CENTER "${prefix}_REG*3"]
MOVE_LABEL "${prefix}_REG" -1mm 2mm
MOVE_LABEL "${prefix}_POWER_OUTPUT" -2mm -8mm
MOVE_LABEL "${prefix}_POWER_INPUT" -2mm -8mm
POP_SETTINGS
}
#
# Use ${prefix}_POWER_INPUT*2 for input, ${prefix}_POWER_OUTPUT*2 for output
#
proc lm_positive_adjustable_power { prefix x y net_input net_output {lm_chip LM338} } {
PUSH_SETTINGS
MOVE_OFFSET $x $y
DEFAULT_STYLE "Power"
DEFAULT_LAYER "solder"
MAKE_RECT {0mm 0mm} {35mm 30mm}
DEFAULT_LAYER "component"
PART "${prefix}_POWER_INPUT" "Power input" 32mm 2.5mm 90 [make_test_point_block 2 1]
make_thermal_h "solder" "Power" "${prefix}_POWER_INPUT*1"
PART "${prefix}_POWER_OUTPUT" "Power output" 3mm 2.5mm 90 [make_test_point_block 2 1]
make_thermal_h "solder" "Power" "${prefix}_POWER_OUTPUT*1"
PART "${prefix}_REG" $lm_chip 15mm 15mm 0 [make_lm338]
PART "${prefix}_H0" "H0" 20mm 2.3mm 0 [make_hole 3.7mm 3mm 0.9mm]
PART "${prefix}_H1" "H1" 20mm 27.7mm 0 [make_hole 3.7mm 3mm 0.9mm]
#
# Use an LED for debugging and as a default load
#
PART "${prefix}_r1" "r1" 4mm 6.5mm 0 [make_0805]
PART "${prefix}_L1" "L1" 10mm 100mil 180 [make_t1]
make_thermal_v "solder" "Power" "${prefix}_L1*1"
CONNECT "$net_output" [list "${prefix}_r1*1" "${prefix}_POWER_OUTPUT*2" "${prefix}_REG*VOUT*"]
CONNECT "$net_input" [list "${prefix}_POWER_INPUT*2"]
CONNECT "GND" [list "${prefix}_L1*1" "${prefix}_POWER_OUTPUT*1" "${prefix}_POWER_INPUT*1" ]
CONNECT "${prefix}_LED1" [list "${prefix}_r1*2" "${prefix}_L1*2"]
MAKE_PATH [LEAD_CENTER "${prefix}_r1*2"] { EN } [LEAD_CENTER "${prefix}_L1*2"]
# Bypass capacitors
PART "${prefix}_c1" "c1" 14.5mm 21.75mm -90 [make_0805]
PART "${prefix}_c2" "c2" 31mm 18mm 180 [make_small_elec_cap]
make_thermal_h "solder" "Power" "${prefix}_c2*1"
PART "${prefix}_c3" "c3" 31mm 26mm 180 [make_small_elec_cap]
make_thermal_h "solder" "Power" "${prefix}_c3*1"
PART "${prefix}_c4" "c4" 12mm 17mm -90 [make_0805]
PART "${prefix}_c5" "c5" 6mm 19mm 0 [make_small_elec_cap]
make_thermal_h "solder" "Power" "${prefix}_c5*1"
PART "${prefix}_c6" "c6" 10mm 26mm 180 [make_small_elec_cap]
make_thermal_h "solder" "Power" "${prefix}_c6*1"
PART "${prefix}_c7" "c7" 5mm 9mm 180 [make_1206]
PART "${prefix}_r3" "r3" 11mm 10.5mm -90 [make_vert_res]
PART "${prefix}_r4" "r4" 5mm 12.5mm 0 [make_vert_res]
PART "${prefix}_r2" "r2" 32mm 10mm 90 [make_vert_res]
MAKE_PATH [LEAD_CENTER "${prefix}_REG*VIN*"] S [LEAD_CENTER "${prefix}_c1*2"]
MAKE_PATH [LEAD_CENTER "${prefix}_REG*VOUT*"] {E S} [LEAD_CENTER "${prefix}_c6*2"]
MAKE_PATH [LEAD_CENTER "${prefix}_REG*VIN*"] {W S} [LEAD_CENTER "${prefix}_c3*2"]
MAKE_PATH [LEAD_CENTER "${prefix}_REG*VADJ*"] E [LEAD_CENTER "${prefix}_r3*1"]
MAKE_PATH [LEAD_CENTER "${prefix}_r4*2"] W [LEAD_CENTER "${prefix}_r3*1"]
MAKE_PATH [LEAD_CENTER "${prefix}_L1*1"] S [LEAD_CENTER "${prefix}_r3*2"]
MAKE_PATH [LEAD_CENTER "${prefix}_c6*1"] {N E} [LEAD_CENTER "${prefix}_c1*1"]
MAKE_PATH [LEAD_CENTER "${prefix}_c7*1"] W [LEAD_CENTER "${prefix}_r3*2"]
MAKE_PATH [LEAD_CENTER "${prefix}_c4*1"] W [LEAD_CENTER "${prefix}_c6*1"]
for { set i 1 } { $i <= 7 } { incr i } {
CONNECT "GND" [list "${prefix}_c$i*1"]
}
CONNECT $net_input [list "${prefix}_r2*1" ]
CONNECT "${prefix}_in" [list "${prefix}_c1*2" "${prefix}_c2*2" "${prefix}_c3*2" "${prefix}_r2*2" "${prefix}_REG*VIN*"]
MAKE_PATH [LEAD_CENTER "${prefix}_POWER_INPUT*2"] {S W} [LEAD_CENTER "${prefix}_r2*1"]
MAKE_PATH [LEAD_CENTER "${prefix}_r2*2"] {W S} [LEAD_CENTER "${prefix}_c2*2"]
CONNECT $net_output [list "${prefix}_c4*2" "${prefix}_c5*2" "${prefix}_c6*2" "${prefix}_c7*2" "${prefix}_r4*1"]
CONNECT "${prefix}_REGADJ" [list "${prefix}_REG*VADJ*" "${prefix}_r3*1" "${prefix}_r4*2"]
CONNECT "GND" [list "${prefix}_r3*2"]
MAKE_PATH [LEAD_CENTER "${prefix}_POWER_OUTPUT*2"] S [LEAD_CENTER "${prefix}_REG*VOUT*"]
MOVE_LABEL "${prefix}_REG" -1mm 2mm
MOVE_LABEL "${prefix}_POWER_OUTPUT" -2mm -8mm
MOVE_LABEL "${prefix}_POWER_INPUT" -2mm -8mm
POP_SETTINGS
}
#
# Use ${prefix}_POWER_INPUT*2 for input, ${prefix}_POWER_OUTPUT*2 for output
#
proc lm_negative_power { prefix x y net_input net_output {lm_chip LM7912} } {
PUSH_SETTINGS
MOVE_OFFSET $x $y
DEFAULT_STYLE "Power"
DEFAULT_LAYER "solder"
MAKE_RECT {0mm 0mm} {35mm 30mm}
DEFAULT_LAYER "component"
PART "${prefix}_POWER_INPUT" "Power input" 32mm 2.5mm 90 [make_test_point_block 2 1]
make_thermal_h "solder" "Power" "${prefix}_POWER_INPUT*1"
PART "${prefix}_POWER_OUTPUT" "Power output" 3mm 2.5mm 90 [make_test_point_block 2 1]
make_thermal_h "solder" "Power" "${prefix}_POWER_OUTPUT*1"
PART "${prefix}_REG" $lm_chip 15mm 15mm 0 [make_to220]
make_thermal_h "solder" "Power" "${prefix}_REG*1"
PART "${prefix}_H0" "H0" 20mm 2.3mm 0 [make_hole 3.7mm 3mm 0.9mm]
PART "${prefix}_H1" "H1" 20mm 27.7mm 0 [make_hole 3.7mm 3mm 0.9mm]
#make_thermal_h "solder" "Power" "${prefix}_H0*1" 5mm
#make_thermal_h "solder" "Power" "${prefix}_H1*1" 5mm
#DEFAULT_LAYER "solder"
#MAKE_PATH [LEAD_CENTER "${prefix}_H0*1"] {E5mm W10mm E5mm} [LEAD_CENTER "${prefix}_H0*1"]
#MAKE_PATH [LEAD_CENTER "${prefix}_H1*1"] {E5mm W10mm E5mm} [LEAD_CENTER "${prefix}_H1*1"]
#
# Use a LED for debugging and as a default load
#
PART "${prefix}_r1" "r1" 4mm 8mm 0 [make_0805]
PART "${prefix}_L1" "L1" 10mm 100mil -90 [make_t1]
make_thermal_h "solder" "Power" "${prefix}_L1*2"
CONNECT "$net_output" [list "${prefix}_r1*1" "${prefix}_POWER_OUTPUT*2" "${prefix}_REG*3"]
CONNECT "$net_input" [list "${prefix}_POWER_INPUT*2" ]
CONNECT "GND" [list "${prefix}_L1*2" "${prefix}_POWER_OUTPUT*1" "${prefix}_POWER_INPUT*1" "${prefix}_REG*1"]
CONNECT "${prefix}_LED1" [list "${prefix}_r1*2" "${prefix}_L1*1"]
MAKE_PATH [LEAD_CENTER "${prefix}_r1*2"] { EN } [LEAD_CENTER "${prefix}_L1*1"]
# Bypass capacitors
PART "${prefix}_c1" "c1" 15mm 8mm 90 [make_0805]
PART "${prefix}_c2" "c2" 31mm 18mm 180 [make_small_elec_cap]
make_thermal_h "solder" "Power" "${prefix}_c2*2"
PART "${prefix}_c3" "c3" 31mm 26mm 180 [make_small_elec_cap]
make_thermal_h "solder" "Power" "${prefix}_c3*2"
PART "${prefix}_c4" "c4" 11mm 16.5mm -90 [make_0805]
PART "${prefix}_c5" "c5" 4mm 20mm 90 [make_small_elec_cap]
make_thermal_h "solder" "Power" "${prefix}_c5*2"
PART "${prefix}_c6" "c6" 10mm 26mm 90 [make_small_elec_cap]
make_thermal_h "solder" "Power" "${prefix}_c6*2"
PART "${prefix}_c7" "c6" 5mm 12mm 0 [make_1206]
PART "${prefix}_r2" "r2" 32mm 10mm 90 [make_vert_res]
MAKE_PATH [LEAD_CENTER "${prefix}_REG*2"] {E2mm N W} [LEAD_CENTER "${prefix}_c1*1"]
MAKE_PATH [LEAD_CENTER "${prefix}_c1*2"] S [LEAD_CENTER "${prefix}_REG*1"]
MAKE_PATH [LEAD_CENTER "${prefix}_c7*2"] {S W} [LEAD_CENTER "${prefix}_c4*2"]
MAKE_PATH [LEAD_CENTER "${prefix}_REG*1"] {E S} [LEAD_CENTER "${prefix}_c4*2"]
MAKE_PATH [LEAD_CENTER "${prefix}_REG*3"] {E S} [LEAD_CENTER "${prefix}_c6*1"]
MAKE_PATH [LEAD_CENTER "${prefix}_REG*2"] {E S} [LEAD_CENTER "${prefix}_c3*1"]
for { set i 1 } { $i <= 7 } { incr i } {
CONNECT "GND" [list "${prefix}_c$i*2"]
}
CONNECT $net_input [list "${prefix}_REG*2" "${prefix}_r2*1"]
CONNECT "${prefix}_in" [list "${prefix}_c1*1" "${prefix}_c2*1" "${prefix}_c3*1" "${prefix}_r2*2"]
CONNECT $net_output [list "${prefix}_c4*1" "${prefix}_c5*1" "${prefix}_c6*1" "${prefix}_c7*1"]
MAKE_PATH [LEAD_CENTER "${prefix}_POWER_INPUT*2"] S [LEAD_CENTER "${prefix}_r2*1"]
MAKE_PATH [LEAD_CENTER "${prefix}_r2*2"] S [LEAD_CENTER "${prefix}_REG*2"]
MAKE_PATH [LEAD_CENTER "${prefix}_POWER_OUTPUT*2"] S [LEAD_CENTER "${prefix}_REG*3"]
MOVE_LABEL "${prefix}_REG" -1mm 2mm
MOVE_LABEL "${prefix}_POWER_OUTPUT" -2mm -8mm
MOVE_LABEL "${prefix}_POWER_INPUT" -2mm -8mm
POP_SETTINGS
}
proc ti_adc_block {prefix x y} {
PUSH_SETTINGS
MOVE_OFFSET $x $y
DEFAULT_STYLE "Power"
DEFAULT_LAYER "solder"
MAKE_RECT {85mm 17mm} {140mm 126.5mm}
MAKE_RECT {70mm 17mm} {135mm 65mm}
MAKE_RECT {50mm 90mm} {135mm 126.5mm}
MAKE_RECT {45mm 5mm} {80mm 20mm}
DEFAULT_LAYER "component"
lm_positive_adjustable_power "${prefix}_3_3V" 100mm 22mm "POS_RAIL" "${prefix}_RAIL_3_3V"
lm_positive_power "${prefix}_5V" 100mm 58mm "POS_RAIL" "${prefix}_RAIL_5V"
lm_positive_power "${prefix}_12V" 100mm 93.5mm "POS_RAIL" "${prefix}_RAIL_12V"
lm_negative_power "${prefix}_NEG12V" 60mm 93.5mm "NEG_RAIL" "${prefix}_RAIL_NEG12V"
MAKE_PATH [LEAD_CENTER "${prefix}_3_3V_POWER_INPUT:*:2"] {E5mm S W} [LEAD_CENTER "${prefix}_5V_POWER_INPUT:*:2"]
MAKE_PATH [LEAD_CENTER "${prefix}_5V_POWER_INPUT:*:2"] {E5mm S W} [LEAD_CENTER "${prefix}_12V_POWER_INPUT:*:2"]
PART "${prefix}_S" "serial interface" 2.5in 0.7in -90 [make_test_point_block 2 10]
PART "${prefix}_PS" "power supply" 3.1in 2.05in 180 [make_test_point_block 2 5]
PART "${prefix}_A" "analog interface" 2.5in 3.4in -90 [make_test_point_block 2 10]
MOVE_LABEL "${prefix}_PS" 0mm 5mm
# CONNECT "${prefix}_RAIL_15V" [list "${prefix}_PS*:1"]
# CONNECT "${prefix}_RAIL_NEG15V" [list "${prefix}_PS*:2"]
# CONNECT "${prefix}_RAIL_3_3V" [list "${prefix}_PS*:9"]
CONNECT "GND" [list "${prefix}_PS:*:5" "${prefix}_PS:*:6" "${prefix}_S*:4" "${prefix}_S*:10" "${prefix}_S*:18"]
make_thermal_h "solder" "Power" "${prefix}_PS*:5"
make_thermal_h "solder" "Power" "${prefix}_PS*:6"
PART "${prefix}_PS2" "power supply breakout" 3.5in 2.05in 180 [make_test_point_block 2 10]
MOVE_LABEL "${prefix}_PS2" 5mm 0mm
make_thermal_h "solder" "Power" "${prefix}_PS2*:1"
make_thermal_h "solder" "Power" "${prefix}_PS2*:2"
make_thermal_h "solder" "Power" "${prefix}_PS2*:19"
make_thermal_h "solder" "Power" "${prefix}_PS2*:20"
CONNECT GND [list "${prefix}_PS2*:1" "${prefix}_PS2*:2" "${prefix}_PS2*:19" "${prefix}_PS2*:20"]
MAKE_PATH [LEAD_CENTER "${prefix}_PS:*:1"] {E4mm N E} [LEAD_CENTER "${prefix}_PS2*:8"]
MAKE_PATH [LEAD_CENTER "${prefix}_PS:*:3"] {E3mm N E} [LEAD_CENTER "${prefix}_PS2*10"]
MAKE_PATH [LEAD_CENTER "${prefix}_PS:*:7"] {E3mm S E} [LEAD_CENTER "${prefix}_PS2*12"]
MAKE_PATH [LEAD_CENTER "${prefix}_PS:*:9"] {E4mm S E} [LEAD_CENTER "${prefix}_PS2*14"]
MAKE_PATH [LEAD_CENTER "${prefix}_PS:*:2"] {W3mm S3mm E8mm N E NE1mm} [LEAD_CENTER "${prefix}_PS2*:6"]
MAKE_PATH [LEAD_CENTER "${prefix}_PS:*:4"] {W5mm S8mm E12mm N E} [LEAD_CENTER "${prefix}_PS2*:4"]
MAKE_PATH [LEAD_CENTER "${prefix}_PS:*:10"] {W3mm N3mm E8mm S E SE1mm} [LEAD_CENTER "${prefix}_PS2*:16"]
MAKE_PATH [LEAD_CENTER "${prefix}_PS:*:8"] {W5mm N8mm E12mm S E} [LEAD_CENTER "${prefix}_PS2*:18"]
CONNECT "${prefix}_VAP" [list "${prefix}_PS:*:1" "${prefix}_PS2*:8"]
CONNECT "${prefix}_5VA" [list "${prefix}_PS:*:3" "${prefix}_PS2*10"]
CONNECT "${prefix}_1_8" [list "${prefix}_PS:*:7" "${prefix}_PS2*12"]
CONNECT "${prefix}_3_3" [list "${prefix}_PS:*:9" "${prefix}_PS2*14"]
CONNECT "${prefix}_VAN" [list "${prefix}_PS:*:2" "${prefix}_PS2*:6"]
CONNECT "${prefix}_N5VA" [list "${prefix}_PS:*:4" "${prefix}_PS2*:4"]
CONNECT "${prefix}_5VD" [list "${prefix}_PS:*:10" "${prefix}_PS2*:16"]
CONNECT "${prefix}_VD1" [list "${prefix}_PS:*:8" "${prefix}_PS2*:18"]
CONNECT "${prefix}_RAIL_12V" [list "${prefix}_PS2*:7"]
CONNECT "${prefix}_RAIL_NEG12V" [list "${prefix}_PS2*:5"]
CONNECT "${prefix}_RAIL_3_3V" [list "${prefix}_PS2*:13"]
CONNECT "${prefix}_RAIL_5V" [list "${prefix}_PS2*:15"]
CONNECT "${prefix}_RAIL_5V" [list "${prefix}_PS2*:9"]
MAKE_PATH [LEAD_CENTER "${prefix}_PS2*:13"] {E5mm WN W} [LEAD_CENTER "${prefix}_3_3V_POWER_OUTPUT:*:2"]
MAKE_PATH [LEAD_CENTER "${prefix}_PS2*:9"] {E8mm SE2mm S SE2mm E} [LEAD_CENTER "${prefix}_5V_POWER_OUTPUT:*:2"]
MAKE_PATH [LEAD_CENTER "${prefix}_PS2*:7"] {E5mm SE2mm S SE2mm E} [LEAD_CENTER "${prefix}_12V_POWER_OUTPUT:*:2"]
MAKE_PATH [LEAD_CENTER "${prefix}_PS2*:5"] {E3mm SE2mm S9mm SW10mm S SW8mm W4mm SW2mm W SW2mm S2mm SW2mm W2mm} [LEAD_CENTER "${prefix}_NEG12V_POWER_OUTPUT:*:2"]
DEFAULT_LAYER "solder"
MAKE_PATH [LEAD_CENTER "${prefix}_PS2*:15"] {E3mm S W} [LEAD_CENTER "${prefix}_PS2*:9"]
DEFAULT_FLAG line ""
MAKE_PATH [LEAD_CENTER "${prefix}_S*:4"] {N3mm S} [LEAD_CENTER "${prefix}_S*:4"]
MAKE_PATH [LEAD_CENTER "${prefix}_S*:10"] {N3mm S} [LEAD_CENTER "${prefix}_S*:10"]
MAKE_PATH [LEAD_CENTER "${prefix}_S*:18"] {N3mm S} [LEAD_CENTER "${prefix}_S*:18"]
foreach k {2 4 8 10} {
foreach {x y} [LEAD_CENTER "${prefix}_PS:*:$k"] {}
PUSH_SETTINGS
PARTS_ON_BACK
PART "${prefix}PSC$k" "bypass_capacitor" [expr $x-[dim2mil 4mm]] $y 0 [make_0805]
DEFAULT_LAYER "solder"
MAKE_PATH [LEAD_CENTER "${prefix}_PS:*:$k"] { E } [LEAD_CENTER "${prefix}PSC$k:*:2"]
make_thermal_v "solder" "Power" "${prefix}PSC$k:*:1"
DEFAULT_STYLE "Power"
CONNECT "GND" "${prefix}PSC$k:*:1"
MOVE_LABEL "${prefix}PSC$k" -2mm -15mm
POP_SETTINGS
}
foreach k {1 3 7 9} {
foreach {x y} [LEAD_CENTER "${prefix}_PS:*:$k"] {}
PUSH_SETTINGS
PARTS_ON_BACK
PART "${prefix}PSC$k" "bypass_capacitor" [expr $x+[dim2mil 4mm]] $y 180 [make_0805]
DEFAULT_LAYER "solder"
MAKE_PATH [LEAD_CENTER "${prefix}_PS:*:$k"] { E } [LEAD_CENTER "${prefix}PSC$k:*:2"]
make_thermal_v "solder" "Power" "${prefix}PSC$k:*:1"
DEFAULT_STYLE "Power"
CONNECT "GND" "${prefix}PSC$k:*:1"
MOVE_LABEL "${prefix}PSC$k" -2mm -15mm
POP_SETTINGS
}
PUSH_SETTINGS
DEFAULT_LAYER "solder"
DEFAULT_STYLE "Power"
MAKE_PATH [LEAD_CENTER "${prefix}PSC2:*:1"] { S } [LEAD_CENTER "${prefix}PSC10:*:1"]
MAKE_PATH [LEAD_CENTER "${prefix}PSC1:*:1"] { S } [LEAD_CENTER "${prefix}PSC9:*:1"]
MAKE_PATH [LEAD_CENTER "${prefix}_PS:*:5"] { E5mm W5mm } [LEAD_CENTER "${prefix}_PS:*:5"]
POP_SETTINGS
# foreach i {2 4 8 10} {
# foreach {x0 y0} [LEAD_CENTER "${prefix}_PS:*:$i"] {}
# PART "${prefix}_PS2C$i" "bypass cap" [expr $x0-[dim2mil 4mm]-[dim2mil $x]] [expr $y0-[dim2mil $y]] 0 [make_0805]
# }
POP_SETTINGS
}
proc so16_proto_pattern { prefix x y } {
PUSH_SETTINGS
MOVE_OFFSET $x $y
DEFAULT_STYLE "Power"
DEFAULT_LAYER "solder"
PART "${prefix}" "SO16" 5mm 5mm 0 [make_SO16]
POP_SETTINGS
}
#VIA "A" 1in 2in
#VIA "" 2in 3in
# Layout board left to right
#
DEFAULT_STYLE "Power"
DEFAULT_LAYER "component"
set i_spacing [list 3.8mm [expr [dim2mil 6in]-[dim2mil 3.8mm]] [expr [dim2mil 11in]+[dim2mil 3.8mm]] [expr [dim2mil 16in]-[dim2mil 3.8mm]]]
set j_spacing [list 3.8mm [expr [dim2mil 5.6in]-[dim2mil 28.8mm]] [expr [dim2mil 5.3in]-[dim2mil 3.8mm]]]
for { set i 0 } { $i < 4 } { incr i } {
for {set j 0 } { $j< 3} { incr j } {
PART "H$i$j" "H$i$j" [lindex $i_spacing $i] [lindex $j_spacing $j] 0 [make_hole 3.7mm 2mm 0.9mm]
}
}
make_thermal_h "solder" "Power" "H21:*1" 5mm
make_thermal_v "solder" "Power" "H21:*1" 5mm
PART "J1" "Hirose FX2-100S" 53mm 8mm 0 [make_hirose_fx2 100]
DEFAULT_LAYER "solder"
#MAKE_RECT {45mm 1mm} {400mm 45mm}
#MAKE_RECT {1mm 1mm} {45mm 133mm}
MAKE_RECT {1mm 1mm} [list [expr [dim2mil 16in]-[dim2mil 1mm]] [expr [dim2mil 5.3in]-[dim2mil 1mm]]]
DEFAULT_STYLE "Power"
MAKE_PATH [LEAD_CENTER "J1:A1:*"] {} [LEAD_CENTER "J1:A2:*"]
MAKE_PATH [LEAD_CENTER "J1:A49:*"] {} [LEAD_CENTER "J1:A50:*"]
MAKE_PATH [LEAD_CENTER "J1:A50:*"] {W5mm NW2mm N NE2mm E} [LEAD_CENTER "J1:B49:*"]
MAKE_PATH [LEAD_CENTER "J1:B5:*"] {} [LEAD_CENTER "J1:B47:*"]
MAKE_PATH [LEAD_CENTER "J1:B6:*"] {} [LEAD_CENTER "J1:B44:*"]
DEFAULT_LAYER "solder"
PUSH_SETTINGS
DEFAULT_FLAG line ""
for { set i 5 } { $i < 45 } { incr i 2 } {
CONNECT "GND" [list "J1:B$i:*" "J1:B[expr $i+1]:*"]
MAKE_PATH [LEAD_CENTER "J1:B$i:*"] {} [LEAD_CENTER "J1:B[expr $i+1]:*"]
MAKE_PATH [LEAD_CENTER "J1:B$i:*"] {N2mm S2mm} [LEAD_CENTER "J1:B$i:*"]
}
DEFAULT_FLAG line ""
MAKE_PATH [LEAD_CENTER "J1:B2:*"] {E5mm W5mm} [LEAD_CENTER "J1:B2:*"]
CONNECT "GND" [list "J1:B2:*" "J1:B45:*" "J1:B47:*"]
POP_SETTINGS
DEFAULT_LAYER "component"
ti_adc_block "A" -1mm 8mm
ti_adc_block "B" 130mm 8mm
ti_adc_block "C" 260mm 8mm
PART "term1" "signal block1" 161mm 5mm 90 [make_test_point_block 2 5]
foreach k {1 3 5 7 9} {
CONNECT "GND" "term1:*:$k"
make_thermal_h "solder" "Power" "term1:*:$k"
}
PART "term2" "signal block2" 22mm 130mm -90 [make_test_point_block 2 5]
foreach k {1 3 5 7 9 } {
CONNECT "GND" "term2:*:$k"
make_thermal_h "solder" "Power" "term2:*:$k"
}
PART "CLOCKS" "in/out clock terminal" 25mm 6.5mm 90 [make_test_point_block 2 5]
foreach k {1 3 5 7 9} {
CONNECT "GND" "CLOCKS:*:$k"
make_thermal_h "solder" "Power" "CLOCKS:*:$k"
}
MOVE_LABEL "term1" 1mm 5mm
MOVE_LABEL "term2" 10mm -3mm
MOVE_LABEL "CLOCKS" -15mm 0mm
#lm_positive_adjustable_power "FPGA_5V" 200mm 1mm "POS_RAIL" "FPGA_RAIL_5V"
if { 0 } {
PART "power_term1" "power terminal" 363mm 10mm 0 [make_test_point_block 5 5]
foreach k {1 6 11 16 21} {
CONNECT "GND" "power_term1:*:$k"
make_thermal_v "solder" "Power" "power_term1:*:$k"
foreach j {1 2 3 4} {
CONNECT "P$k" [list "power_term1:*:[expr $k+$j]"]
}
MAKE_PATH [LEAD_CENTER "power_term1:*:[expr $k+1]"] {W} [LEAD_CENTER "power_term1:*:[expr $k+4]"]
}
MOVE_LABEL "power_term1" -5mm 5mm
}
#PART "proto1" "prototyping area" 320mm 10mm 90 [make_test_point_block 6 12]
#PART "proto2" "prototyping area" 9.5mm 55mm 0 [make_test_point_block 6 12]
#MOVE_LABEL "proto1" -4mm 6mm
#MOVE_LABEL "proto2" -4mm 14mm
DEFAULT_STYLE "Signal"
set i 6
foreach k {10 8 6 4} {
foreach {x y} [LEAD_CENTER "term1:*:$k"] {}
PUSH_SETTINGS
PARTS_ON_BACK
PART "term1r$k" "termination resistor" $x [expr $y+[dim2mil 5mm]] -90 [make_0805]
DEFAULT_LAYER "solder"
MAKE_PATH [LEAD_CENTER "term1:*:$k"] { S } [LEAD_CENTER "term1r$k:*:2"]
make_thermal_h "solder" "Power" "term1r$k:*:1"
DEFAULT_STYLE "Power"
CONNECT "GND" "term1r$k:*:1"
MOVE_LABEL "term1r$k" 0mm [expr $k*0.9]mm
POP_SETTINGS
CONNECT "term1_$k" [list "term1:*:$k" "J1:A$i:*" "term1r$k:*:2"]
MAKE_PATH [LEAD_CENTER "term1:*:$k"] [list S2mm SW[expr 8.5-0.5*$k]mm W NW2mm N] [LEAD_CENTER "J1:A$i:*"]
incr i
}
set useful_pins {1 3 5 7 9 11 13 17}
foreach block {B} {
set k 0
foreach pin $useful_pins {
foreach {x y} [LEAD_CENTER "${block}_S:*:$pin"] {}
PUSH_SETTINGS
PARTS_ON_BACK
PART "${block}_Sr$k" "termination resistor" $x [expr $y+[dim2mil 5mm]] -90 [make_0805]
DEFAULT_LAYER "solder"
MAKE_PATH [LEAD_CENTER "${block}_S:*:$pin"] { S } [LEAD_CENTER "${block}_Sr$k:*:2"]
make_thermal_h "solder" "Power" "${block}_Sr$k:*:1"
DEFAULT_STYLE "Power"
CONNECT "GND" "${block}_Sr$k:*:1"
MOVE_LABEL "${block}_Sr$k" 0mm [expr $k*0.9+2]mm
POP_SETTINGS
CONNECT "${block}_S$k" [list "${block}_S:*:$pin" "J1:A$i:*" "${block}_Sr$k:*:2"]
MAKE_PATH [LEAD_CENTER "${block}_S:*:$pin"] [list S1mm SW[expr 2+1.3*$k]mm W NW22mm W50mm NW2mm N] [LEAD_CENTER "J1:A$i:*"]
incr i
incr k
}
}
foreach block {C} {
set k 0
foreach pin $useful_pins {
foreach {x y} [LEAD_CENTER "${block}_S:*:$pin"] {}
PUSH_SETTINGS
PARTS_ON_BACK
PART "${block}_Sr$k" "termination resistor" $x [expr $y+[dim2mil 5mm]] -90 [make_0805]
DEFAULT_LAYER "solder"
MAKE_PATH [LEAD_CENTER "${block}_S:*:$pin"] { S } [LEAD_CENTER "${block}_Sr$k:*:2"]
make_thermal_h "solder" "Power" "${block}_Sr$k:*:1"
DEFAULT_STYLE "Power"
CONNECT "GND" "${block}_Sr$k:*:1"
MOVE_LABEL "${block}_Sr$k" 0mm [expr $k*0.9+2]mm
POP_SETTINGS
CONNECT "${block}_S$k" [list "${block}_S:*:$pin" "J1:A$i:*" "${block}_Sr$k:*:2"]
MAKE_PATH [LEAD_CENTER "${block}_S:*:$pin"] [list S[expr 1+$k]mm SW2mm W[expr 33+1.27*$pin+0.5*$k]mm NW15mm W[expr 37-$k]mm SW30mm W NW26.5mm W50mm NW2mm N] [LEAD_CENTER "J1:A$i:*"]
incr i
incr k
}
}
foreach block { A} {
set k 0
foreach pin $useful_pins {
foreach {x y} [LEAD_CENTER "${block}_S:*:$pin"] {}
PUSH_SETTINGS
PARTS_ON_BACK
PART "${block}_Sr$k" "termination resistor" $x [expr $y+[dim2mil 5mm]] -90 [make_0805]
DEFAULT_LAYER "solder"
MAKE_PATH [LEAD_CENTER "${block}_S:*:$pin"] { S } [LEAD_CENTER "${block}_Sr$k:*:2"]
make_thermal_h "solder" "Power" "${block}_Sr$k:*:1"
DEFAULT_STYLE "Power"
CONNECT "GND" "${block}_Sr$k:*:1"
MOVE_LABEL "${block}_Sr$k" 0mm [expr $k*0.9+2]mm
POP_SETTINGS
CONNECT "${block}_S$k" [list "${block}_S:*:$pin" "J1:A$i:*" "${block}_Sr$k:*:2"]
MAKE_PATH [LEAD_CENTER "${block}_S:*:$pin"] [list S[expr 8-$k]mm SE2mm E NE2mm N] [LEAD_CENTER "J1:A$i:*"]
incr i
incr k
}
}
foreach k {10 8 6 4 2} {
foreach {x y} [LEAD_CENTER "term2:*:$k"] {}
PUSH_SETTINGS
PARTS_ON_BACK
PART "term2r$k" "termination resistor" $x [expr $y-[dim2mil 5mm]] 90 [make_0805]
DEFAULT_LAYER "solder"
MAKE_PATH [LEAD_CENTER "term2:*:$k"] { S } [LEAD_CENTER "term2r$k:*:2"]
make_thermal_h "solder" "Power" "term2r$k:*:1"
DEFAULT_STYLE "Power"
CONNECT "GND" "term2r$k:*:1"
MOVE_LABEL "term2r$k" 0mm [expr -$k*0.9-3]mm
POP_SETTINGS
CONNECT "term2_$k" [list "term2:*:$k" "J1:A$i:*" "term2r$k:*:2"]
MAKE_PATH [LEAD_CENTER "term2:*:$k"] [list N[expr 115-0.5*$k]mm NE2mm E NE2mm N] [LEAD_CENTER "J1:A$i:*"]
incr i
}
puts stderr "Last used automatic A pin: A$i"
foreach k {2 4 6 8 10} {
foreach {x y} [LEAD_CENTER "CLOCKS:*:$k"] {}
PUSH_SETTINGS
PARTS_ON_BACK
PART "clocksr$k" "termination resistor" $x [expr $y+[dim2mil 5mm]] 270 [make_0805]
DEFAULT_LAYER "solder"
MAKE_PATH [LEAD_CENTER "CLOCKS:*:$k"] { E } [LEAD_CENTER "clocksr$k:*:2"]
make_thermal_h "solder" "Power" "clocksr$k:*:1"
DEFAULT_STYLE "Power"
CONNECT "GND" "clocksr$k:*:1"
MOVE_LABEL "clocksr$k" 3mm -1mm
POP_SETTINGS
}
for { set i 6 } { $i < 42 } { incr i } {
foreach {x y} [LEAD_CENTER "J1:A$i:*"] {}
PUSH_SETTINGS
PARTS_ON_BACK
PART "Jr$i" "termination resistor" $x 12.5mm -90 [make_0603]
DEFAULT_LAYER "solder"
MAKE_PATH [LEAD_CENTER "J1:A$i:*"] { S } [LEAD_CENTER "Jr$i:*:2"]
DEFAULT_FLAG line ""
MAKE_PATH [LEAD_CENTER "Jr$i:*:1"] { S2mm N2mm } [LEAD_CENTER "Jr$i:*:1"]
#make_thermal_h "solder" "Power" "Jr$i:*:1"
DEFAULT_STYLE "Power"
CONNECT "GND" "Jr$i:*:1"
MOVE_LABEL "Jr$i" 0mm [expr ($i-6) % 6+2]mm
POP_SETTINGS
}
CONNECT "clock2" {"CLOCKS:*:2" "clocksr2:*:2"}
CONNECT "fx2_clkin" {"CLOCKS:*:4" "J1:B46:*" "clocksr4:*:2"}
CONNECT "fx2_clkio" {"CLOCKS:*:6" "J1:B48:*" "clocksr6:*:2"}
CONNECT "fx2_clkout" {"CLOCKS:*:8" "J1:A47:*" "clocksr8:*:2"}
CONNECT "CLOCKS10" {"CLOCKS:*:10" "J1:A40:*" "clocksr10:*:2"}
MAKE_PATH [LEAD_CENTER "J1:B46:*"] { N3.3mm NW1mm W20mm SW2mm S5.5mm SW2mm W NW2mm N } [LEAD_CENTER "CLOCKS:*:4"]
MAKE_PATH [LEAD_CENTER "J1:B48:*"] { N2.5mm NW1mm W15mm SW2mm S5.5mm SW2mm W NW2mm N } [LEAD_CENTER "CLOCKS:*:6"]
MAKE_PATH [LEAD_CENTER "J1:A47:*"] { S3.5mm SW1mm W NW2mm N } [LEAD_CENTER "CLOCKS:*:8"]
MAKE_PATH [LEAD_CENTER "J1:A40:*"] { S2.5mm SW1mm W NW2mm N } [LEAD_CENTER "CLOCKS:*:10"]
PART "LED1" "low current led" 12mm 130mm 0 [make_t1]
DEFAULT_STYLE "Power"
CONNECT "GND" "LED1:*:1"
make_thermal_v "solder" "Power" "LED1:*:1"
DEFAULT_STYLE "Signal"
PART "LED1r1" "current limiter" 14mm 126mm 0 [make_0805]
CONNECT "LED1s" {"LED1:*:2" "LED1r1:*:1"}
MAKE_PATH [LEAD_CENTER "LED1:*:2"] {S W} [LEAD_CENTER "LED1r1:*:1"]
CONNECT "term2_2" {"LED1r1:*:2"}
MAKE_PATH [LEAD_CENTER "LED1r1:*:2"] {S W} [LEAD_CENTER "term2r2:*:2"]
#
# General power supply connections
#
DEFAULT_LAYER "component"
DEFAULT_STYLE "Power"
MAKE_PATH [LEAD_CENTER "A_12V_POWER_INPUT:*:2"] {E5mm S18mm E20mm SE2mm S7.5mm SE2mm E NE2mm N W5mm} [LEAD_CENTER "B_12V_POWER_INPUT:*:2"]
MAKE_PATH [LEAD_CENTER "B_12V_POWER_INPUT:*:2"] {E5mm S18mm E25mm SE2mm S7.5mm SE2mm E NE2mm N W5mm} [LEAD_CENTER "C_12V_POWER_INPUT:*:2"]
DEFAULT_LAYER "solder"
MAKE_PATH [LEAD_CENTER "A_NEG12V_POWER_INPUT:*:2"] {E3mm SE2mm S27mm E42mm NE2mm N7mm NE2mm E15mm SE2mm S7mm SE2mm E N NW2mm W3mm} [LEAD_CENTER "B_NEG12V_POWER_INPUT:*:2"]
MAKE_PATH [LEAD_CENTER "B_NEG12V_POWER_INPUT:*:2"] {E3mm SE2mm S27mm E47mm NE2mm N7mm NE2mm E15mm SE2mm S7mm SE2mm E N NW2mm W3mm} [LEAD_CENTER "C_NEG12V_POWER_INPUT:*:2"]
PART "pt1" "power terminal" 243mm 7mm 90 [make_terminal_block3]
make_thermal_v "solder" "Power" "pt1:*:2" 4mm
PART "d1" "input power diode" 265mm 6mm 0 [make_large_diode]
PART "d2" "input power diode" 265mm 14mm 180 [make_large_diode]
DEFAULT_LAYER "component"
MAKE_PATH [LEAD_CENTER "pt1:*:1"] {N NE2mm E } [LEAD_CENTER "d1:*:1"]
MAKE_PATH [LEAD_CENTER "pt1:*:3"] {S SE2mm E } [LEAD_CENTER "d2:*:2"]
foreach i { 2 3 4 5 6 } {
PART "ipt$i" "internal power terminal" [expr 267+$i*20]mm 7mm 90 [make_terminal_block3]
make_thermal_v "solder" "Power" "ipt$i:*:2" 4mm
}
DEFAULT_LAYER "component"
MAKE_PATH [LEAD_CENTER "d1:*:2"] {SE4mm E NE2mm N NE2mm E S4mm } [LEAD_CENTER "ipt2:*:1"]
MAKE_PATH [LEAD_CENTER "d2:*:1"] {E NE2mm N } [LEAD_CENTER "ipt2:*:3"]
foreach i { 2 3 4 5 } {
MAKE_PATH [LEAD_CENTER "ipt$i:*:1"] {N4mm E S4mm } [LEAD_CENTER "ipt[expr $i+1]:*:1"]
MAKE_PATH [LEAD_CENTER "ipt$i:*:3"] {S4mm E N4mm } [LEAD_CENTER "ipt[expr $i+1]:*:3"]
}
MAKE_PATH [LEAD_CENTER "ipt6:*:3"] {S4mm E SE2mm S W5mm} [LEAD_CENTER "C_3_3V_POWER_INPUT:*:2"]
DEFAULT_LAYER "solder"
MAKE_PATH [LEAD_CENTER "ipt6:*:1"] {E4mm SE2mm S SW2mm W N27mm NW2mm W3mm} [LEAD_CENTER "C_NEG12V_POWER_INPUT:*:2"]
#PART "clkio_r" "term resistor" 32mm 10mm -90 [make_vert_res]
#PART "clkio_r" "term resistor" 32mm 10mm -90 [make_vert_res]
#so16_proto_pattern "D" 300mm 5mm
puts stderr "****** Do not forget to mark board revision"
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