power_supply.tcl
global skip_missed_pins
set skip_missed_pins 1
#
# Unspecified dimensions are in 1/100 mil
#
source "library.tcl"
PCB "power_supply_1" 11cm 5cm
DRC space 10mil width 12mil overlap 5mil silkwidth 8mil
#
# The board uses only 2 layers, however pcb wants two extra for silk and rat lines
#
LAYERS total 4 solder {1} component {2} names {
1 "solder"
2 "component"
}
#STYLE "Signal" thickness 11mil diameter 60mil hole 36mil
STYLE "Signal" thickness 12mil diameter 48mil hole 24mil
STYLE "Power" thickness 1mm diameter 60mil hole 36mil
STYLE "Fat" thickness 25mil diameter 60mil hole 36mil
STYLE "Skinny" thickness 10mil diameter 36mil hole 24mil
STYLE "Signal_via" thickness 12mil diameter 36mil hole 20mil
# Use ${prefix}_POWER_INPUT*2 for input, ${prefix}_POWER_OUTPUT*2 for output
#
proc lm_positive_adjustable_power { prefix x y net_input net_output {lm_chip LM338} } {
PUSH_SETTINGS
MOVE_OFFSET $x $y
DEFAULT_STYLE "Power"
DEFAULT_LAYER "solder"
MAKE_RECT {0mm 0mm} {35mm 30mm}
DEFAULT_LAYER "component"
PART "${prefix}_POWER_INPUT" "Power input" 2mm 2.5mm 90 [make_test_point_block 2 1]
make_thermal_h "solder" "Power" "${prefix}_POWER_INPUT*1"
PART "${prefix}_POWER_OUTPUT" "Power output" 30mm 2.5mm 90 [make_test_point_block 2 1]
make_thermal_h "solder" "Power" "${prefix}_POWER_OUTPUT*1"
PART "${prefix}_REG" $lm_chip 18mm 22mm 90 [make_lm338]
PART "${prefix}_H0" "H0" 5.3mm 27mm 0 [make_hole 3.7mm 3mm 0.9mm]
PART "${prefix}_H1" "H1" 30.7mm 27mm 0 [make_hole 3.7mm 3mm 0.9mm]
CONNECT "$net_output" [list "${prefix}_POWER_OUTPUT*2" "${prefix}_REG*VOUT*"]
CONNECT "$net_input" [list "${prefix}_POWER_INPUT*2"]
CONNECT "GND" [list "${prefix}_POWER_OUTPUT*1" "${prefix}_POWER_INPUT*1" ]
# Bypass capacitors
PART "${prefix}_c1" "c1" 14.5mm 18mm 90 [make_0805]
PART "${prefix}_c2" "c2" 10mm 11mm 90 [make_small_elec_cap]
make_thermal_h "solder" "Power" "${prefix}_c2*1"
PART "${prefix}_c3" "c3" 7.5mm 19mm 0 [make_small_elec_cap]
make_thermal_h "solder" "Power" "${prefix}_c3*1"
PART "${prefix}_c4" "c4" 17.5mm 13.5mm 0 [make_0805]
PART "${prefix}_c6" "c6" 31.5mm 14.5mm 180 [make_small_elec_cap]
make_thermal_h "solder" "Power" "${prefix}_c6*1"
PART "${prefix}_c5" "c5" 17.5mm 10mm 0 [make_1206]
PART "${prefix}_r4" "r4" 20mm 17mm 180 [make_vert_res]
PART "${prefix}_r2" "r2" 2mm 11mm 90 [make_vert_res]
PART "${prefix}_r3" "r3" 30mm 20.5mm 0 [make_vert_res]
make_thermal_h "solder" "Power" "${prefix}_r3*2"
PART "${prefix}_r1" "r1" 23mm 10mm -90 [make_vert_res]
PART "${prefix}_l1" "l1" 23mm 3mm 90 [make_t1]
make_thermal_h "solder" "Power" "${prefix}_l1*1"
MAKE_PATH [LEAD_CENTER "${prefix}_r2*1"] {NW} [LEAD_CENTER "${prefix}_r2*2"]
MAKE_PATH [LEAD_CENTER "${prefix}_REG*VIN*"] {NW} [LEAD_CENTER "${prefix}_c1*2"]
MAKE_PATH [LEAD_CENTER "${prefix}_r4*1"] {SW} [LEAD_CENTER "${prefix}_REG*VADJ*"]
MAKE_PATH [LEAD_CENTER "${prefix}_r4*2"] {S} [LEAD_CENTER "${prefix}_REG*VOUT*"]
MAKE_PATH [LEAD_CENTER "${prefix}_c3*2"] {S 1mm SE E} [LEAD_CENTER "${prefix}_REG*VIN*"]
MAKE_PATH [LEAD_CENTER "${prefix}_r4*2"] NE [LEAD_CENTER "${prefix}_c4*2"]
MAKE_PATH [LEAD_CENTER "${prefix}_c2*2"] {SE S E} [LEAD_CENTER "${prefix}_REG*VIN*"]
MAKE_PATH [LEAD_CENTER "${prefix}_r2*1"] {SE} [LEAD_CENTER "${prefix}_POWER_INPUT*2"]
MAKE_PATH [LEAD_CENTER "${prefix}_r2*2"] E [LEAD_CENTER "${prefix}_c2*2*"]
MAKE_PATH [LEAD_CENTER "${prefix}_c4*2"] NE [LEAD_CENTER "${prefix}_c5*2"]
MAKE_PATH [LEAD_CENTER "${prefix}_r1*1"] {SW} [LEAD_CENTER "${prefix}_c4*2"]
MAKE_PATH [LEAD_CENTER "${prefix}_r1*1"] {SE} [LEAD_CENTER "${prefix}_c6*2"]
MAKE_PATH [LEAD_CENTER "${prefix}_r1*2"] {N} [LEAD_CENTER "${prefix}_l1*2"]
MAKE_PATH [LEAD_CENTER "${prefix}_c6*2"] {E S} [LEAD_CENTER "${prefix}_POWER_OUTPUT*2"]
MAKE_PATH [LEAD_CENTER "${prefix}_r3*1"] SW [LEAD_CENTER "${prefix}_REG*VADJ*"]
MAKE_PATH [LEAD_CENTER "${prefix}_c1*1"] {NW N W} [LEAD_CENTER "${prefix}_c2*1"]
MAKE_PATH [LEAD_CENTER "${prefix}_c4*1"] {NW} [LEAD_CENTER "${prefix}_c5*1"]
MAKE_PATH [LEAD_CENTER "${prefix}_c5*1"] {NW} [LEAD_CENTER "${prefix}_c2*1"]
for { set i 1 } { $i <= 6 } { incr i } {
CONNECT "GND" [list "${prefix}_c$i*1"]
}
CONNECT "GND" [list "${prefix}_r3*2" "${prefix}_l1*1"]
CONNECT $net_input [list "${prefix}_r2*1" ]
CONNECT "${prefix}_in" [list "${prefix}_c1*2" "${prefix}_c2*2" "${prefix}_c3*2" "${prefix}_r2*2" "${prefix}_REG*VIN*"]
CONNECT $net_output [list "${prefix}_c4*2" "${prefix}_c6*2" "${prefix}_c5*2" "${prefix}_r4*2" "${prefix}_r1*1"]
CONNECT "${prefix}_REGADJ" [list "${prefix}_REG*VADJ*" "${prefix}_r4*1" "${prefix}_r3*1"]
MOVE_LABEL "${prefix}_REG" -1mm 2mm
MOVE_LABEL "${prefix}_POWER_OUTPUT" -2mm -8mm
MOVE_LABEL "${prefix}_POWER_INPUT" -2mm -8mm
POP_SETTINGS
}
proc lm_positive_constant_current_adjustable_power { prefix x y net_input net_output {lm_chip LM338} } {
PUSH_SETTINGS
MOVE_OFFSET $x $y
DEFAULT_STYLE "Power"
DEFAULT_LAYER "solder"
MAKE_RECT {0mm 0mm} {35mm 30mm}
DEFAULT_LAYER "component"
PART "${prefix}_POWER_INPUT" "Power input" 2mm 2.5mm 90 [make_test_point_block 2 1]
make_thermal_h "solder" "Power" "${prefix}_POWER_INPUT*1"
PART "${prefix}_POWER_OUTPUT" "Power output" 30mm 2.5mm 90 [make_test_point_block 2 1]
make_thermal_h "solder" "Power" "${prefix}_POWER_OUTPUT*1"
PART "${prefix}_REG" $lm_chip 18mm 22mm 90 [make_lm338]
PART "${prefix}_H0" "H0" 5.3mm 27mm 0 [make_hole 3.7mm 3mm 0.9mm]
PART "${prefix}_H1" "H1" 30.7mm 27mm 0 [make_hole 3.7mm 3mm 0.9mm]
CONNECT "$net_output" [list "${prefix}_POWER_OUTPUT*2" "${prefix}_REG*VADJ*"]
CONNECT "$net_input" [list "${prefix}_POWER_INPUT*2"]
CONNECT "GND" [list "${prefix}_POWER_OUTPUT*1" "${prefix}_POWER_INPUT*1" ]
# Bypass capacitors
PART "${prefix}_c1" "c1" 14.5mm 18mm 90 [make_0805]
PART "${prefix}_c2" "c2" 12.5mm 11mm 90 [make_small_elec_cap]
make_thermal_h "solder" "Power" "${prefix}_c2*1"
PART "${prefix}_c3" "c3" 7.5mm 18mm 0 [make_small_elec_cap]
make_thermal_h "solder" "Power" "${prefix}_c3*1"
PART "${prefix}_c4" "c4" 24.5mm 22mm 180 [make_0805]
make_thermal_h "solder" "Power" "${prefix}_c4*1"
PART "${prefix}_c6" "c6" 26.5mm 11.5mm 180 [make_small_elec_cap]
make_thermal_h "solder" "Power" "${prefix}_c6*1"
PART "${prefix}_c5" "c5" 25mm 19mm 180 [make_1206]
PART "${prefix}_r4" "r4" 18mm 15.5mm 90 [make_vert_res]
PART "${prefix}_r2" "r2" 2mm 11mm 90 [make_vert_res]
PART "${prefix}_d1" "d1" 7mm 6mm -90 [make_vert_diode]
MAKE_PATH [LEAD_CENTER "${prefix}_REG*VIN*"] {NW} [LEAD_CENTER "${prefix}_c1*2"]
MAKE_PATH [LEAD_CENTER "${prefix}_r4*1"] {E S} [LEAD_CENTER "${prefix}_REG*VADJ*"]
MAKE_PATH [LEAD_CENTER "${prefix}_REG*VOUT*"] {E S} [LEAD_CENTER "${prefix}_r4*2"]
MAKE_PATH [LEAD_CENTER "${prefix}_c3*2"] {S 1mm SE E} [LEAD_CENTER "${prefix}_REG*VIN*"]
MAKE_PATH [LEAD_CENTER "${prefix}_c4*2"] W [LEAD_CENTER "${prefix}_REG*VADJ*"]
MAKE_PATH [LEAD_CENTER "${prefix}_c2*2"] {S} [LEAD_CENTER "${prefix}_REG*VIN*"]
MAKE_PATH [LEAD_CENTER "${prefix}_POWER_INPUT*2"] E [LEAD_CENTER "${prefix}_d1*2"]
MAKE_PATH [LEAD_CENTER "${prefix}_d1*1"] SW [LEAD_CENTER "${prefix}_r2*1"]
MAKE_PATH [LEAD_CENTER "${prefix}_r2*2"] E [LEAD_CENTER "${prefix}_c2*2*"]
MAKE_PATH [LEAD_CENTER "${prefix}_c4*2"] N [LEAD_CENTER "${prefix}_c5*2"]
MAKE_PATH [LEAD_CENTER "${prefix}_c5*2"] NE [LEAD_CENTER "${prefix}_c6*2"]
MAKE_PATH [LEAD_CENTER "${prefix}_c6*2"] {N NE} [LEAD_CENTER "${prefix}_POWER_OUTPUT*2"]
MAKE_PATH [LEAD_CENTER "${prefix}_c1*1"] {N W} [LEAD_CENTER "${prefix}_c2*1"]
MAKE_PATH [LEAD_CENTER "${prefix}_c4*1"] {NE} [LEAD_CENTER "${prefix}_c5*1"]
MAKE_PATH [LEAD_CENTER "${prefix}_c5*1"] {NE} [LEAD_CENTER "${prefix}_c6*1"]
for { set i 1 } { $i <= 6 } { incr i } {
CONNECT "GND" [list "${prefix}_c$i*1"]
}
CONNECT $net_input [list "${prefix}_d1*2" ]
CONNECT "${prefix}_in2" [list "${prefix}_c1*2" "${prefix}_c2*2" "${prefix}_c3*2" "${prefix}_r2*2" "${prefix}_REG*VIN*"]
CONNECT "${prefix}_in1" [list "${prefix}_d1*1" "${prefix}_r2*1"]
CONNECT $net_output [list "${prefix}_c4*2" "${prefix}_c6*2" "${prefix}_c5*2"]
CONNECT $net_output [list "${prefix}_r4*1"]
CONNECT "${prefix}_out1" [list "${prefix}_REG*VOUT*" "${prefix}_r4*2"]
MOVE_LABEL "${prefix}_REG" -1mm 2mm
MOVE_LABEL "${prefix}_POWER_OUTPUT" -2mm -8mm
MOVE_LABEL "${prefix}_POWER_INPUT" -2mm -8mm
POP_SETTINGS
}
proc bypass_adjustable_power { prefix x y net_input {transistor FJA4310} } {
PUSH_SETTINGS
MOVE_OFFSET $x $y
DEFAULT_STYLE "Power"
DEFAULT_LAYER "solder"
MAKE_RECT {0mm 0mm} {27mm 30mm}
DEFAULT_LAYER "component"
PART "${prefix}_POWER_INPUT" "Power input" 13mm 2.5mm 90 [make_test_point_block 2 1]
make_thermal_h "solder" "Power" "${prefix}_POWER_INPUT*1"
PART "${prefix}_t1" $transistor 13mm 22.09mm 90 [make_fja4310]
PART "${prefix}_H0" "H0" 0.3mm 27mm 0 [make_hole 3.7mm 3mm 0.9mm]
PART "${prefix}_H1" "H1" 25.7mm 27mm 0 [make_hole 3.7mm 3mm 0.9mm]
PART "${prefix}_r1" "r1" 25mm 9mm 90 [make_vert_res]
PART "${prefix}_d1" "Z 7V" 23mm 17mm 90 [make_vert_diode]
PART "${prefix}_r2" "r2" 18mm 13mm -90 [make_vert_res]
make_thermal_h "solder" "Power" "${prefix}_r2*2"
PART "${prefix}_r3" "r3" 8mm 13mm -90 [make_vert_res]
make_thermal_h "solder" "Power" "${prefix}_r3*2"
MAKE_PATH [LEAD_CENTER "${prefix}_r1*1"] E [LEAD_CENTER "${prefix}_POWER_INPUT*2"]
MAKE_PATH [LEAD_CENTER "${prefix}_r1*2"] {ES} [LEAD_CENTER "${prefix}_d1*1"]
MAKE_PATH [LEAD_CENTER "${prefix}_d1*2"] {S W} [LEAD_CENTER "${prefix}_t1*BASE*"]
MAKE_PATH [LEAD_CENTER "${prefix}_r2*1"] {E S} [LEAD_CENTER "${prefix}_t1*BASE*"]
MAKE_PATH [LEAD_CENTER "${prefix}_r3*1"] S [LEAD_CENTER "${prefix}_t1*EMITTER*"]
MAKE_PATH [LEAD_CENTER "${prefix}_POWER_INPUT*2"] S [LEAD_CENTER "${prefix}_t1*COLLECTOR*"]
CONNECT "GND" [list "${prefix}_r2*2" "${prefix}_r3*2" "${prefix}_POWER_INPUT*1"]
CONNECT $net_input [list "${prefix}_r1*1" "${prefix}_t1*COLLECTOR*" "${prefix}_POWER_INPUT*2"]
MOVE_LABEL "${prefix}_t1" -1mm 2mm
MOVE_LABEL "${prefix}_POWER_INPUT" -2mm -8mm
POP_SETTINGS
}
#VIA "A" 1in 2in
#VIA "" 2in 3in
# Layout board left to right
#
DEFAULT_STYLE "Power"
DEFAULT_LAYER "component"
set i_spacing [list 3.8mm [expr [dim2mil 11cm]-[dim2mil 3.8mm]]]
set j_spacing [list 3.8mm [expr [dim2mil 5cm]-[dim2mil 3.8mm]]]
for { set i 0 } { $i < [llength $i_spacing] } { incr i } {
for {set j 0 } { $j< [llength $j_spacing]} { incr j } {
PART "H$i$j" "H$i$j" [lindex $i_spacing $i] [lindex $j_spacing $j] 0 [make_hole 3.7mm 2mm 0.9mm]
}
}
DEFAULT_LAYER "solder"
MAKE_RECT {2mm 2mm} {108mm 48mm}
DEFAULT_LAYER "component"
lm_positive_adjustable_power "POS" 72mm 13mm cc_output vpos
lm_positive_constant_current_adjustable_power "CCPOS" 3mm 13mm power_input cc_output
bypass_adjustable_power "BPS" 42mm 13mm cc_output
MAKE_PATH [LEAD_CENTER "CCPOS_POWER_OUTPUT*2"] E [LEAD_CENTER "BPS_POWER_INPUT*2"]
MAKE_PATH [LEAD_CENTER "BPS_POWER_INPUT*2"] E [LEAD_CENTER "POS_POWER_INPUT*2"]
puts stderr "****** Do not forget to mark board revision"
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