* Overview

* Hw_script
* Preload
* Musplay
* Mixer
* Cdman
* Tgt-edif
* fx2_programmer
* Software Radio
* LIGO viewer
* DAQ system

* Status
* Download

* About me

Tgt-edif is an EDIF 2.0.0 output module for Icarus verilog compiler. At the moment it has been tested to produce output for Atmel AT40K devices.

What works:

  • all logic primitives
  • some lpm devices:
    • adder
    • dff
    • mux (select width 1)
  • all constants

You can access tgt-edif sourcecode from Sourceforge CVS, cvs module name is tgt-edif.

Getting it to work with your FPGA

Would you like tgt-edif to produce output consumable by your place and route tool? All your need to do is to create a custom *.inc file - take a look at and for examples. Also, you will find in CVS two sample verilog files addc.v and sample.v which you can run through a synthesizer to produce sample netlists that will work for your chip.


  • Tue Jul 10 14:25:33 2001 Now all logic works.
  • Mon Jul 09 15:29:25 2001 Finished a big rewrite. tgt-edif now outputs flat netlists.
  • Sun Aug 05 05:35:26 2001 First cut at support for Xilinx Spartan II fpgas
  • Sun Aug 05 05:51:13 2001 Added instructions to README on adding support for new FPGAs.

SourceForge Logo was last modified
Warning: date(): It is not safe to rely on the system's timezone settings. You are *required* to use the date.timezone setting or the date_default_timezone_set() function. In case you used any of those methods and you are still getting this warning, you most likely misspelled the timezone identifier. We selected the timezone 'UTC' for now, but please set date.timezone to select your timezone. in /home/project-web/volodya-project/htdocs/ on line 15
4:16pm Monday, April 22nd 2002