* About me
Tgt-edif is an EDIF 2.0.0 output module for Icarus verilog compiler. At the moment it has been tested to produce output for Atmel AT40K devices.
You can access tgt-edif sourcecode from Sourceforge CVS, cvs module name is tgt-edif.
Getting it to work with your FPGAWould you like tgt-edif to produce output consumable by your place and route tool? All your need to do is to create a custom *.inc file - take a look at atmel_at40k.inc and xilinx_spartan.inc for examples. Also, you will find in CVS two sample verilog files addc.v and sample.v which you can run through a synthesizer to produce sample netlists that will work for your chip.
http://volodya-project.sourceforge.net/tgt-edif.php was last modified
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4:16pm Monday, April 22nd 2002